This study unit deals with the computer architecture and development tools related to embedded systems. The study unit is further divided into the following two parts:
Computer architecture for ES
Microcontrollers and FPGAs are generally low-powered devices that are small in size to fit in e.g., edge computing context. Although such devices are beneficial for their computing efficiency in terms of chip area and power consumption, they are resource-constraint, e.g., they have limited memory and processing speed. In this course, the focus will be given to the micro-architecture and the higher levels of computing hierarchy.
Learning objectives
The student can:
- explain and differentiate the architectures suitable for embedded systems
- describe the re-configurable architectures for embedded systems
Modelling and synthesis of architectures
Modelling and synthesis tools are utilized to realize computing architectures. Hardware Descriptive Languages (HDL) enable modelling of architectures. The HDL models serve as input to the synthesis tools to map the desired architectures on the target devices.
Learning objectives
The student can:
- model embedded architectures using a hardware description language like VHDL
- perform timing verification of models using contemporary tools like Quartus
- perform synthesis of models to implement architectures on embedded devices
- describe and perform high-level synthesis of architectures for embedded devices
Assessment
Assignment 1 (30%)
Assignment 2 (0%)
Assignment 3 (0%)
Assignment 4 (30%)
Written test (40%)
The grades for assignment 2 and assignment 3 must be sufficient.
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