Kies de Nederlandse taal
Course module: 202001137
Digital Hardware
Course info
Course module202001137
Credits (ECTS)6
Course typeStudy Unit
Language of instructionEnglish
Contact personir. E. Molenkamp
ir. E. Molenkamp
ir. E. Molenkamp
Contactperson for the course
ir. E. Molenkamp
Academic year2021
Starting block
Application procedureYou apply via OSIRIS Student
Registration using OSIRISYes
The student:
  • can work with datasheets and based on these calculate timing aspects (setup time, hold time, maximum clock frequency) for basic circuits
  • knows how to handle asynchronous inputs
  • knows how to use an asynchronous FIFO in multiple clock domains
  • has a basic understanding of fault models (e.g. single stuck-at, multiple stuck-at faults, bridging faults)
  • can manually derive test patterns for the single stuck-at fault model
  • understands built-in-self-test (BIST)
  • understands the internal structure of a programmable logic (PLA, PAL, FPGA)
  • understands the simulation model of VHDL
  • can model combinational logic in VHDL
  • can model sequential logic, including finite state machines, in VHDL
  • can model hardware using a subset of VHDL for synthesis
  • can use a synthesis tool to program an FPGA
  • understands the timing aspects of a synthesis tool (e.g. setting timing constraints, and understand the timing reports)
  • can work in a team (participate actively in group activities, accepts directions and feedback, is able to deal with problems that occur within such a team in a professional manner)
  • can design a system based on a list of requirements and explain how the design complies with these requirements
  • can motivate design choices
  • can make a structured and detailed test plan system and application
  • can document the system and application
Digital Hardware gives a deeper insight in hardware aspects. Subjects are timing, metastability, synchronisation, the hardware description language VHDL and the realisation of a digital system on an FPGA. A project is part of DH.

The DH grade is determined by a lab that must be successfully completed before the written test, a written test (grade must be larger or equal 5.5) and a final project (grade must be larger or equal 5.5). Grade DH = 0.7xgrade written test + 0.3xgrade final project.
Module 5
Participating study
Bachelor Electrical Engineering
Required materials
Recommended materials
To be announced
Instructional modes
Presence dutyYes

Presence dutyYes

Labs, Test(s) and Project

The lab assignments must be completed before the written examination

Kies de Nederlandse taal