|
After the course the student can (in the context of a case):
- Use a top-down design flow for designing a synthesizable data path with controller via:
- a paper specification,
- a behavioral description,
- algorithms
- data path and controller
- use a hardware description language (VHDL) to support the design steps.
- describe a suitable test strategy
- develop and apply assertion-based verification by using the Property Specification Language (PSL)
- formulate several design alternatives and motivate the design decisions
|
|
|
In the different phases of the design of a digital system, the hardware description language VHDL is used. This language is also used in industry.
During the first two weeks, students will become familiar with this language. This includes the simulation and synthesis aspects (realization with a FPGA (Field Programmable Gate Array)).
During the remainder of the course a case (the design of a processor) is used to practice the design process. In general there a design constraints, e.g. speed, power, area. The exploration of design alternatives is essential in the course. Part of this is also an introduction in low power aspects.
Due to the increasing complexity of digital systems verification is important. Assertion-based verification is used to verify the design steps. To support this VHDL is extended with the language PSL (Property Specification Language). This also requires a well-chosen test strategy, including an introduction in the Open Source VHDL Verification Methodology (OSVVM).
You will need your laptop during the lab sessions.
|
 |
|