Kies de Nederlandse taal
Course module: 191210860
Advanced Electronics Project
Course info
Course module191210860
Credits (ECTS)5
Course typeCourse
Language of instructionEnglish
Contact persondr. H.S. Bindra
dr. H.S. Bindra
Contactperson for the course
dr. H.S. Bindra
Examiner E.A.M. Klumperink
Examiner M.S. Oude Alink
Academic year2022
Starting block
Application procedureYou apply via OSIRIS Student
Registration using OSIRISYes
Train electronic circuit design, modeling, simulation, layout skills with awareness of the parasitic effects of design on signals in a practical application scenario.  
This project trains modeling, design, simulation, layout, circuit implementation and interfacing skills that are important for practical electronic circuit design. The training is done individually. The most important skills to be trained are:
  1. Making a motivated choice of a circuit topology, starting from desired functional behavior.
  2. Choosing component parameters and biasing to meet a set of performance requirements (e.g. transfer function, distortion, noise). This involves analysis skills and goal oriented problem solving. Gaining insight in the available degrees of freedom in the design, and in the design trade-offs is crucial, using hand calculations, verified by computer simulations.
  3. Analyzing and coping with practical circuit realization problems related to wiring parasitics, imperfect power supplies and grounding and interfering signals. Layout verified by design rule compliance (DRC) checking and layout versus schematic (LVS) checking and parasitic circuit extraction and re-simulation.
  4. Dealing with testability: define sufficient inputs and outputs for testability, model the interface to the outside world including parasitics related to Electrostatic Static Discharge protections, latchup precautions, bondpads, bondwires, packaging, and auxiliary circuits for test and measurements.
After the training, a design project follows involving:
  1. Small-Signal Analysis of design blocks,
  2. creating test benches for evaluating performance and specification compliance of the design block,
  3. Layout design with parasitic awareness,
  4. Layout versus schematic verification with root-cause analysis for encountered performance bottlenecks,
  5. Analysis of degradation in performance if any due to imperfect supply and connections to the external world. 
Final design report in the form of a presentation. After a final oral discussion along with the ppt, the overall project results will be graded.
Assumed previous knowledge
M3 EE Electronics (202100150), M4 EE Wireless Transmission (202100135), and M11 EE Electronic System Design (202100253).

Knowledge about transistor (MOSFET), its characteristics, region of operation, and its small-signal analysis is recommended.
Participating study
Master Electrical Engineering
Required materials
Recommended materials
Course guide
Project manual
Instructional modes
Project unsupervised
Presence dutyYes

Design Report, Presentation

Kies de Nederlandse taal