Learn to design and test a mixed-signal SoC at different levels of hierarchy
The SoC design course focuses on design skills necessary for the realization of a System-on-Chip that consists of software, analog and digital hardware. Participating chairs are CAES and ICD. The course starts with three modules that deal with different aspects of SoC design. These modules (60 hours each) consist of lectures, hands-on training and practical exercises:
HDL-Based SoC Design. This module covers: VHDL for simulation and synthesis, distinction between combinational and sequential logic, partitioning of hardware in data path and control, (manual) architectural synthesis, systems with a processor and hardware-software co-design. The main tools are Modelsim for VHDL simulation and Synopsys Design Compiler for VHDL synthesis.
Physical SoC and IP Design and Testing. Topics covered by this module include: power and clock distribution, digital circuit design at the transistor and layout levels focusing on adder structures, fault modeling, automatic test pattern generation, scan chains core-based testing, JTAG and P1500. For circuit design the Tanner tool suite is used.
Mixed-Signal SoC Design. This module deals with: mixed-signal design basics, noise and mismatch modeling, packaging and parasitics, analog building blocks and power efficiency. The main tool used is LT-Spice.
The course concludes with a 100 hour design project that covers all of the areas above. Topic of the project is an audio system. Realization will include digital-to-analog and analog-to-digital conversion, microprocessor-based control using the LEON processor, dedicated digital signal processing peripherals for hardware acceleration of some functions, and a test strategy. Although an SoC realization is kept in mind, the project uses an FPGA platform for prototyping using an Altera Cyclone development kit.
|Inschrijvingseisen:Master students||Verplicht materiaal-Aanbevolen materiaal|
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